Coprocessor Support

ARM9 derivatives are supported (almost no ARM7 derivative features a coprocessor).
Coprocessor 15 registers can be displayed and altered (using Special Function Register windows). Coprocessor 15 is used for cache and MMU implementations.

Cache Support

HiTOP supports both derivatives with fixed (e.g. ARM920T) and variable (e.g. ARM926) cache size.
An enabled cache does not prevent debugging. This requires special handling of breakpoints and memory writes by the debugger. For instance, after changes to the memory took place (e.g. caused by the download of an application), the instruction cache is invalidated automatically. This prevents outdated instructions from the instruction cache being used instead of the actual memory content. This is completely transparent for the user during normal operation; an initial setting in the Processor Settings Dialog is sufficient.

MMU Support

The registers of the Memory Management Unit (MMU) can be displayed and altered (using Special Function Register windows).
Debugging with enabled MMU is possible if the virtual address is equal to the physical address. In many practical cases, this prerequisite is met, because the MMU is enabled only to make use of the cache (an enabled MMU is a prerequisite for using the cache). In this case, the MMU often establishes direct address mapping (i.e. virtual address == physical address).