National Semiconductor's CompactRISC architecture was created from the ground up as an alternative solution to CISC and other accumulator based architectures. The CompactRISC architecture is a RISC architecture specifically designed for embedded systems. It features the best of RISC and CISC with compact code generation, low power consumption, silicon-efficient implementations, the ability to tightly integrate on-chip acceleration, I/O and memory functions.
CompactRISC implementations greatly reduce the amount of silicon required for the CPU, code memory and data memory, without significantly reducing the overall performance advantages of RISC. In addition, because any processing core is only as good as its peripheral support, several key architectural decisions were made to optimize bus structures and I/O control for embedded systems in order to improve flexibility and reduce costs.
Since its introduction, the CompactRISC architecture has firmly established itself by filling a previously unmet market gap - those embedded applications that require the performance of RISC, but cannot afford the processing and cost overhead of 32-bit RISC implementations. The 16-bit CompactRISC family of cores have been particularly popular with designers because of their optimal balance of cost and performance, plus the ability to combine a very small size core with other key on-chip functions.

The CompactRISC architecture enables RISC processors to be optimized for performance, power consumption and die size, bringing the significant advantages of RISC to the embedded systems market. Using the CompactRISC architectures, embedded RISC processors are cost effective, memory efficient, silicon efficient and higher performance. Key RISC advantages include a streamlined instruction set optimized for high-level language compilers; single-cycle instruction execution; and fast, multistage pipeline structures. To this the CompactRISC processors add compact code generation, low-cost silicon implementations and a scaleable processor family that spans the range from 8-bit, to 16-bit, to 32-bit and to 64-bit versions.
The CompactRISC architecture was created from the ground up as a scalable architecture, covering the 16-bit embedded processor domain, while providing the best of RISC (Reduced Instruction Set Computer) and CISC (Complex Instruction Set Computer) architectures. The CompactRISC architecture is enhanced with some typical CISC features, like variable instruction set and direct memory bit manipulation to make it even more effective for embedded applications. A CompactRISC core delivers high performance while maintaining low power consumption, small die size and high code density. Through its modular bus architecture the CompactRISC technology allows designers to build performance-tailored functionality around the CompactRISC core. A separate bus for the on-chip peripheral allows a system-on-a-chip designer to use the same on-chip peripherals and I/O with all CompactRISC derivatives. With common processor architecture and software development tools a software designer can feel comfortable to write identical code for any of the CompactRISC cores.