The high-end controller, which is based on the ARMv8-A architecture, is equipped with four powerful Cortex- A53 cores, a Cortex-M4 boot core and additional accelerator units. Originally designed specifically for image recognition and processing for advanced driver assistance systems (ADAS), the device is also suitable for other computation-intensive applications in the automotive sector due to the Cortex-A53 platform. It also meets the ASIL C requirements of the ISO 26262 standard for functional safety.
Using the powerful hardware-based debugging functions of UDE, both the Cortex-A53 cores and the Cortex-M4 core of the S32V234 are accessible and controllable within a common, consistent user interface. Among other things, the multicore run control management of the UDE, already established for 32-bit multicore systems, is also available for this device. It allows the user to stop almost synchronously either all or a userdefined set of the Cortex-A53 cores either manually or via breakpoints, whereby the Cortex-M4 boot core is always stopped due to the hardware. From this point, a synchronous single stepping is possible or the
execution can be continued completely. For shared code executed by multiple cores, the UDE provides multicore breakpoints for simplifying debugging. Multicore breakpoints always take effect regardless of which
core is currently executing the particular code.
The UDE supports both the AArch32 and AArch64 execution modes of the Cortex-A53 cores. UDE considers the current execution modes even if individual cores are working in different modes. This enables
simultaneous debugging of AArch32 and AArch64 code.
A combined target adapter is provided for the access devices of PLS’ Universal Access Device (UAD) family which enables the debug access to the various available S32V234 development boards. It ensures reliable
and fast communication with the SoC via JTAG or the ARM-specific Serial Wire Debug (SWD) interface. For challenging environmental conditions, this adapter is also optionally available with additional galvanic isolation.