For the control of a multi-core target, the UDE enables the synchronization of two or more cores to so-called run control groups in order to define common start and stop or common individual step. This also includes the extensive use of existing on-chip trigger and synchronization options of various device manufacturers. The consistent user interface ensures the greatest possible flexibility when controlling a multi-core target, without the need to know the underlying on-chip logic in detail.
Features of the multi-core workbench
- Multi-core debugging target manager to select cores and functional units for debugging Core- or user-specific visibility groups in UDE Open Platform including core specific coloring
- Multi-core program loader to distribute binary pattern and select core-specific symbol information
- Graphical code coverage analysis allows of structural coverage to fulfill ISO26262 requirements
- Profiling functions based on instruction pointer trace data from On-chip Emulators (MCDS and SPU) including AURORA trace, Nexus, ETM, ETB, TMC, instruction pointer snooping or simulator output
- The Universal Emulation Configurator (UEC) describes measuring tasks for on-chip emulators
- Parallel test of software for multiple cores independently of their architecture within one user interface
- Synchronization of multiple cores for the debugging (common start and stop) and parallel visualization of context information after synchronized program execution
- Graphical visualization of variables from programs of different cores as time-based two-dimensional diagram in a common view
- The central management for download and distribution of software from one or more ELF files to multiple cores
- Multi-core trace with common analysis and visualization of executed program and data accesses in one or more views of the development user interface.