Control of a multi-core system and debugging is carried out with the UDE in a consistently designed user interface. Universal Multicore Workbench is a new add-on of the well-known modular Universal Debug Engine. With its outstanding features it helps developers of software for multicore SoC's to make your work more easily, clearly and efficiently.
The concept is enhanced by visibility groups for windows of individual cores or freely according to user requirements definable collections of debugger views. Various compiler concepts for multi-core targets are supported by the implemented multi-core / multi-program loader. It enables the separate loading of memory images and symbolic information from the output files of the compiler, specifically for each individual core.
For the control of a multi-core target, the UDE enables the synchronization of two or more cores to so-called run control groups in order to define common start and stop or common individual step. This also includes the extensive use of existing on-chip trigger and synchronization options of various device manufacturers. The consistent user interface ensures the greatest possible flexibility when controlling a multi-core target, without the need to know the underlying on-chip logic in detail.
For the control of a multicore target, the UDE enables the synchronization of two or more cores to so-called run control groups in order to define common start and stop or common individual step. This also includes the extensive use of existing on-chip trigger and synchronization options of various device manufacturers. The consistent user interface ensures the greatest possible flexibility when controlling a multicore target, without the need to know the underlying on-chip logic in detail.
For simple processing of the large amounts of data, which occur when tracing several sources, the UDE is equipped with a multicore trace framework that on the one hand allows conventional troubleshooting on the basis of the recorded data and on the other hand offers various statistical analyses such as profiling analysis and code coverage.
With help of the target manager cores and functional units can be specifically selected for debugging. In order to also be able to retain an overview with several cores, debugger window tabs and toolbars are core-specifically colored.
The concept is enhanced by visibility groups for windows of individual cores or freely according to user requirements definable collections of debugger views. Various compiler concepts for multicore targets are supported by the implemented multicore / multiprogram loader. It enables the separate loading of memory images and symbolic information from the output files of the compiler, specifically for each individual core.
Universal Access Device 3+ (UAD3+) sets new standards in multi-core/multi-target debugging and in high end real-time trace. The UAD3+ is based on a modular concept and offers high -speed debug access to TriCore and PowerArchitecture and further MCU architectures. Multiple JTAG extender pods can be connected via a long cable to ensure a flexible adaptation with the target connector. The UAD3+ is designed for best on class performance.
The Universal Access Device 3+ allows the recording of real-time trace information via a high speed serial trace based interface.
In summary the Universal Multicore Workbench is a new development tool which strongly optimizes the debugging and test of software for multiccore SoC's.
In practice the new Universal Multicore Workbench is used for the first time for the new multicore microcontrollers for automotive applications which were published at the end of last year from Infineon and Joint Development Program from Freescale and STMicroelectronics.
These new multicore devices are milestones for the real-time efficiency of automotive applications. They contain three processor cores which are connected in such a way by a crossbar that they are running with full speed and without any access conflict. Further the implementation contains some FLASH modules and an easy to use and powerful micro programmable Timer Module (up to 8 micro cores) which relieves the main CPU's by nearly independent generation of engine control signals. These devices demand new concepts and debugging functions for development of engine control unit (ECU) software.
The new functions for test of multicore software running on up to 5 cores (three main cores, micro programmable Timer Module and Security Core) in hard real time will used for the first time for power train (engine and transmission control) by the market leaders for ECU's.