HighTec Development Platform

The HighTec Development Platform includes powerful wizards and supports the latest derivatives such as the new TriCore multi-core architectures. It manages the project settings and the entire build process for compiler, assembler and linker, and, moreover, the initialization settings of the hardware. The development platform includes:

  • Project management
  • Setup wizards
  • Version control
  • Model-driven graphical memory layout configuration

The Eclipse™-based Development Platform allows simple definition of projects. After having selected a particular microcontroller derivative, the generation of a project with a correct startup code, the necessary hardware initialization, a valid and appropriate memory layout, and header files that describe the actual hardware configuration, e.g. special function registers, can be prompted virtually at the push of a button. The project contains a simple main function, which allows the implementation to be started immediately. The memory layout can easily be adapted by means of the model-driven GUI in Eclipse™. This configuration will be verified against the derivative memory layout and will assist customers in placing the code and data in the appropriate regions of the memory.


  • HighTec's C/C++ multi-architecture and multi-core compiler suite with leading optimization technology
  • Support of architecture specific function blocks like GTM/MCS and HSM module
  • Eclipse IDE with extended project settings and graphical interface for linker description configuration


  • Multi-core support (ISO and EABI compliant)
  • Long-term support and maintenance service
  • Latest optimisation strategies
  • Code compaction (reverse inlining)
  • Global optimisation strategies
  • Module-based grouping of data to minimize load address operation
  • Options per file and source code fragments
  • Optimised for Auto-Coding
  • Commercial standard and math libraries (no open source)
  • AUTOSAR MCAL driver support

The the HighTec Development Platform is used by leading Tier1 and OEM.

HighTec Development Platform is used by leading Tier1 and OEM

Advanced Multi-Core

HighTec's compiler suite supports homogeneous as well as heterogeneous multi-core architectures. HighTec's solution integrates multi-core support at linker level, making source code adaption unnecessary. This ISO- and EABI-compliant multi-core support makes it easy to port existing single-core based source code to a multi-core system. The user can easily assign executable code or data to the appropriate core at linker level. Data exchange between different cores is handled by the hide-and-visibility concept, which specifies user-defined interfaces between the cores at linker level. Data and code have to be explicitly specified in order to be visible for any other cores than the one they belong to. Any data or code that is shared between cores, is listed in a separate output file and can be used to analyse the cross-reference between the cores. The hide-and-visibility feature implies a reduction of complexity in distributed systems, resulting in a reduced debugging effort and improved maintainability of the software system as a whole. Apart from this, the execution of independent applications on each core is supported, since separation of the code and data is assured, unless otherwise specified by the user. A core can access its local resources, e.g. RAM, via a local address space. In addition, these resources are mapped into a global address space, so that they can be accessed by the other cores. Memory can thus be accessed by different addresses, depending on whether the local address space or the global address space is used. This is also valid for different core architectures such as the GTM/MCS module. The HighTec TriCore linker automatically handles the remapping of memories even for heterogeneous multi-cores. The linker is able to interlink object files for different core architectures and to generate one resulting output elf file.
HighTec tools also support different core architectures such as GTM/MCS (timer module) and HSM security module. The binaries of the TriCore, GTM and HSM can be linked into one ELF file and uploaded 'en bloc' to the target system.
Efficient addressing modes, such as small addressing mode, can be used separately for each core. The corresponding address registers of each core must be initialized in the start-up code. The linker will automatically initialize the necessary base register for the small addressable areas of each core. In summary:

  • Hide-and-visibility concept - interfaces between cores on linker level
  • The proprietary solution for migrating to multi-core
  • Application code can be ported to multi-core without source code modification
  • Proven software can be easily migrated to multi-core silicon
  • Based on linker level (ISO and EABI compliant) - a proprietary solution for migrating to multi-core
  • Core-ID information stored as meta-information on sections and in objects; easy extract info by analyzing symbol table
  • Support of homogenous and heterogeneous Multi-Core architectures

Supported architectures with special features


  • TriCore and AURIX support
  • PCP-C, HSM and GTM/MCS compiler
  • SIMD and FPU support
  • Addressing modes: absolute, register relative, circular
  • Position Independent Code (PIC) and Data (PID)

Power Architecture

  • Freescale - Qorivva MPC55xx, MPC56xx, MPC57xx
  • STMicroelectronics SPC56x, SPC57x
  • VLE, SPE and LSP support
  • Small Data Pointer functionality: about 20% code and run-time improvement
  • SIMD and FPU support
  • GTM/MCS support
  • Position Independent Code (PIC) and Data (PID)


  • High-speed floating-point unit (FPU)
  • Inter-procedural optimizations
  • Multiple-Memory Models: Normal data, Small data, Zero data and tiny data


  • Thumb2 instruction set
  • VFP support
  • Cortex M3/M4 support