FPGA Multicore Emulation

FPGA-based Multicore Microprocessor Emulation

What is it about?

Hitex has enabled Infineon to expedite development of its AURIX multicore 32-bit microcontroller (MCU) architecture by developing a complete FPGA real-time microprocessor simulation platform, Meridian.

The project was realized from Hitex Uk.

This multicore architecture is the foundation of Infineon’s next generation MCU family for automotive powertrain and safety applications. The multicore architecture features up to three processor cores to share the application load, includes lockstep cores and contains further enhanced safety mechanisms to support applications up to ISO 26262 ASIL-D. As this is a major step in a fast-moving market, it was vital for Infineon to be able to prove as much as possible before real silicon was available. We thought it would be interesting for engineers to share our experiences in such an interesting challenge – from both hardware and software perspectives.

Debugging the chicken and the egg

Traditionally, it has only been possible to develop the debugger once the silicon was available, but without the debugger, it wasn’t possible to test the debug interface! The Meridian microprocessorsimulator platform  allowed a new approach to debugging: where the debugging could previously only be carried out once the silicon was available, the Hitex HiTOP debugger was developed using the FPGA multicore simulation before arrival of the real silicon, so that Hitex could ensure that HiTOP could meet the challenge of debugging multiple processing cores on a single chip. For instance, in a single core system there is normally only one entity to be debugged via one JTAG connection; the Meridian platform, however, also supports multicore configurations, so every JTAG command needs to specify the target core as well, implying some routing and arbitration. The debugger needs to be able to connect to the specific core under test and differentiate between them.

These first versions of multicore compilers and debuggers, targeted at multicore applications, are now available to selected partners for evaluation.

Safety first

A vital part of Infineon’s automotive microcontroller strategy is to incorporate advanced features needed for safety-critical systems, such as ECC on internal buses and RAM together with new IP blocks to monitor bus accesses, memory violations etc. The Meridian board has the ability to test these, and also includes a CIC61508 Safety Monitor intelligent watchdog device, so that the dedicated safety IP can be proven and developed (hardware and software) before the real silicon is available. Obviously, with something as valuable as an entire microcontroller’s IP, it was necessary to protect the FPGA image from being reverse-engineered. This means that every image, stored on a simple SD card, is encrypted using an AES 128-bit encryption key; a matching key is blown into the FPGA as a one-time programmable operation. Losing the key is not an option – it would render the £8000 FPGA useless for future images!

What next?

Hitex and Infineon are still exploring the benefits of the Meridian platform – it is already being used for EU-funded research projects into new safety-critical architectures and power control systems. The approach is complementary to other software based simulation tools, so provides Infineon with a generic platform to further tune and experiment with future architectures, all in pursuit of  maximising performance and building architectures that are right first time.