The Hitex RISC-V Knowledge Lab brings together technology experts, innovators, and decision-makers to explore one of the most exciting developments in semiconductor and embedded systems design.
Whether you are evaluating RISC-V for future projects, planning migration paths, or looking for practical insights, the Knowledge Lab provides expert perspectives covering hardware, software, tools, debugging, virtualization, safety, and security.
Join us for seven expert sessions exploring the future of RISC-V development.
Agenda:
- Kickoff Keynote with Thomas Schneid,
Vice President Software and Ecosystem Management (Infineon) - Next Generation AURIX™ | Redefining Real-Time Control and Compute (Infineon)
- RISC-V Migration Services and Enablement (Hitex)
- Compiling the Future of Automotive | HighTec's RISC-V Toolchain for SDVs (HighTec EDV Systeme)
- Shift-Left Debugging for RISC-V | From Simulation to Silicon (PLS)
- Virtual Prototype | Proof of Concept (Hitex)
- Bringing Safety and Security to RISC-V Platforms (Hitex)
Knowledge Lab Facts:
- Date: November 26, 2026
- Time: Starts at 3:00 p.m. CET
- Format: 7 concise, short presentations by experts
- Who?: Infineon, HighTec, PLS, Hitex