Ready for RISC-V: Preparing for the Next Generation of Embedded Systems
Ready for RISC-V
Hitex Knowledge Lab 2026

Hitex RISC-V Knowledge Lab 2026

Preparing for the Next Generation of Embedded Systems

Join leading experts for an exclusive deep dive into RISC-V, its growing ecosystem, and the opportunities it creates across embedded systems, industrial applications, and next-generation products.

The Hitex RISC-V Knowledge Lab brings together technology experts, innovators, and decision-makers to explore one of the most exciting developments in semiconductor and embedded systems design.

Knowledge Lab facts

  • Date: November 26, 2026
  • Time: Starts at 3:00 p.m. CET
  • Format: 7 concise, short presentations by experts
  • Who: Partners include: Infineon, Hightec, PLS

Join us in discovering the future of microcontroller development, including new applications, emerging opportunities, development tools, migration strategies, and real-world examples! Register now and help shape the future of embedded systems!

Register now for free

Across a series of focused expert sessions, our speakers will share insights into RISC-V architectures, software ecosystems, security, functional safety, industrial applications, and emerging trends. The event will culminate in an executive keynote highlighting the strategic importance of open architectures and their role in shaping the future of innovation.

Whether you are an engineer, architect, project leader, or technology strategist, the RISC-V Knowledge Lab offers valuable perspectives, practical knowledge, and an opportunity to connect with the rapidly growing RISC-V community.

Agenda November 26

3:00 p.m. Welcome and Keynote
Opportunities and challenges of RISC-V

  • Thomas Schneid, Vice President Software and Ecosystem Management (Infineon Technologies)

3:20 p.m. Session 1
Next Generation AURIX™: Redefining Real-Time Control and Compute

  • Michael Arzberger, Director of Product Marketing for Automotive and Industrial Microcontrollers (Infineon Technologies)

3:40 p.m. Session 2
RISC-V Migration Services and Enablement

  • Michael Weiss & Matthias Spranz (Hitex GmbH)

4:00 p.m. Session 3
Compiling the Future of Automotive: HighTec’s RISC-V Toolchain for SDV

  • Daniel Sepulveda, HighTec EDV Systeme

4:20 p.m. Session 4
Shift-left Debugging for RISC-V: From Simulation to Silicon

  • Jens Braunes (PLS)

4:40 p.m. Session 5
Proof of Concept with Virtual Prototype

  • Field Application Engineer (Hitex)

5:00 p.m. Session 6
Bringing Safety and Security to RISC-V Platforms

  • Michael Weiss & Matthias Spranz (Hitex GmbH)


Participants can ask questions throughout the presentations using the webinar tool. Questions of interest to everyone will be answered during the Q&A afterwards, while any remaining questions will be addressed in a follow-up email.