Ready for RISC-V: Preparing for the Next Generation of Embedded Systems
Ready for RISC-V
Hitex Knowledge Lab 2026

Hitex RISC-V Knowledge Lab 2026

Preparing for the Next Generation of Embedded Systems

Join leading experts for an exclusive deep dive into RISC-V, its growing ecosystem, and the opportunities it creates across embedded systems, applications, and next-generation products.

The Hitex RISC-V Knowledge Lab is an online event that brings together technology experts, innovators, and decision-makers to explore one of the most exciting developments in semiconductor and embedded systems design.

Knowledge Lab facts

  • Date: November 26, 2026
  • Time: Starts at 3:00 p.m. CET
  • Format: online, 7 concise presentations
  • Who: Partners include: Infineon, Hightec, PLS

Join us in discovering the future of microcontroller development, including development tools and migration strategies. Register now for free!

Register now for free

Across a series of focused expert sessions, our speakers will share insights into RISC-V architectures, software ecosystems, security, and functional safety. The event opens with a keynote by Thomas Schneid, Vice President Software and Ecosystem Management at Infineon Technologies, who will explore the opportunities and challenges of RISC-V, the strategic importance of open architectures, and their role in driving future innovation.

Whether you are an engineer, architect, project leader, or technology strategist, the RISC-V Knowledge Lab offers valuable perspectives and practical knowledge for your next development decisions – conveniently online.

Agenda November 26

3:00 p.m. Welcome and Keynote
Opportunities and challenges of RISC-V

  • Thomas Schneid, Vice President Software and Ecosystem Management (Infineon Technologies)

3:20 p.m. Session 1
Next Generation AURIX™: Redefining Real-Time Control and Compute

  • Michael Arzberger, Director of Product Marketing for Automotive and Industrial Microcontrollers (Infineon Technologies)

3:40 p.m. Session 2
RISC-V Migration Services and Enablement

  • Michael Weiss & Matthias Spranz (Hitex)

4:00 p.m. Session 3
Compiling the Future of Automotive: HighTec’s RISC-V Toolchain for SDV

  • Daniel Sepulveda (HighTec EDV-Systeme)

4:20 p.m. Session 4
Shift-left Debugging for RISC-V: From Simulation to Silicon

  • Jens Braunes (PLS)

4:40 p.m. Session 5
Proof of Concept with Virtual Prototype

  • Field Application Engineer (Hitex)

5:00 p.m. Session 6
Bringing Safety and Security to RISC-V Platforms

  • Michael Weiss & Matthias Spranz (Hitex)


Participants can ask questions throughout the presentations using the webinar tool. Questions of interest to everyone will be answered during the Q&A afterwards, while any remaining questions will be addressed in a follow-up email.

 

Register now for free